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DC Field | Value | Language |
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dc.contributor.author | Hierons, RM | - |
dc.contributor.author | Turker, U | - |
dc.date.accessioned | 2016-02-18T11:55:36Z | - |
dc.date.available | 2016-02-18T11:55:36Z | - |
dc.date.issued | 2016 | - |
dc.identifier.citation | IEEE Transactions on Computers, Forthcooming, (2016) | en_US |
dc.identifier.issn | 0018-9340 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/document/7415960 | - |
dc.identifier.uri | https://bura.brunel.ac.uk/handle/2438/12126 | - |
dc.description | © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | - |
dc.description.abstract | Many automated finite state machine (FSM) based test generation algorithms require that a characterising set (CS) or a set of harmonised state identifiers (HSIs) is first produced.The only previously published algorithms for partial FSMs were brute-force algorithms with exponential worst case time complexity. This paper presents polynomial time algorithms and also massively parallel implementations of both the polynomial time algorithms and the brute-force algorithms. In the experiments the parallel algorithms scaled better than the sequential algorithms and took much less time. Interestingly, while the parallel version of the polynomial time algorithm was fastest for most sizes of FSMs, the parallel version of the brute-force algorithm scaled better due to lower memory requirements. | en_US |
dc.description.sponsorship | This work was supported by The Scientific and Technological Research Council of Turkey (TUBITAK) under grant 1059B191400424 and by the NVIDIA corporation. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
dc.subject | Software engineering/software/program verification | en_US |
dc.subject | Software engineering/testing and debugging | en_US |
dc.subject | Software engineering/test design | en_US |
dc.subject | Finite state machine | en_US |
dc.subject | Characterising sets | en_US |
dc.subject | Harmonised state identifiers | en_US |
dc.subject | General purpose graphics processing units | en_US |
dc.title | Parallel algorithms for generating harmonised state identifiers and characterising sets | en_US |
dc.type | Article | en_US |
dc.identifier.doi | https://doi.org/10.1109/TC.2016.2532869 | - |
dc.relation.isPartOf | IEEE Transactions on Computers | - |
pubs.publication-status | Accepted | - |
pubs.publication-status | Accepted | - |
pubs.publication-status | Accepted | - |
dcterms.rights | © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | - |
Appears in Collections: | Dept of Computer Science Research Papers |
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