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DC Field | Value | Language |
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dc.contributor.author | Liu, L | - |
dc.contributor.author | Chen, N | - |
dc.contributor.author | Meng, H | - |
dc.contributor.author | Zhang, L | - |
dc.contributor.author | Wang, Z | - |
dc.contributor.author | Chen, H | - |
dc.date.accessioned | 2011-11-25T09:30:28Z | - |
dc.date.available | 2011-11-25T09:30:28Z | - |
dc.date.issued | 2004 | - |
dc.identifier.citation | IEEE Journal of Solid-State Circuits, 39(11), 2032 - 2040, Nov 2004 | en_US |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.other | http://ieeexplore.ieee.org/search/freesrchabstract.jsp?tp=&arnumber=1347334&queryText%3DA+VLSI+architecture+of+JPEG2000+encoder%26openedRefinements%3D*%26searchField%3DSearch+All | - |
dc.identifier.uri | http://bura.brunel.ac.uk/handle/2438/6018 | - |
dc.description | Copyright @ 2004 IEEE | en_US |
dc.description.abstract | This paper proposes a VLSI architecture of JPEG2000 encoder, which functionally consists of two parts: discrete wavelet transform (DWT) and embedded block coding with optimized truncation (EBCOT). For DWT, a spatial combinative lifting algorithm (SCLA)-based scheme with both 5/3 reversible and 9/7 irreversible filters is adopted to reduce 50% and 42% multiplication computations, respectively, compared with the conventional lifting-based implementation (LBI). For EBCOT, a dynamic memory control (DMC) strategy of Tier-1 encoding is adopted to reduce 60% scale of the on-chip wavelet coefficient storage and a subband parallel-processing method is employed to speed up the EBCOT context formation (CF) process; an architecture of Tier-2 encoding is presented to reduce the scale of on-chip bitstream buffering from full-tile size down to three-code-block size and considerably eliminate the iterations of the rate-distortion (RD) truncation. | en_US |
dc.description.sponsorship | This work was supported in part by the China National High Technologies Research Program (863) under Grant 2002AA1Z1420 | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE | en_US |
dc.subject | VLSI | en_US |
dc.subject | JPEG2000 | en_US |
dc.subject | Image Compression | en_US |
dc.title | A VLSI architecture of JPEG2000 encoder | en_US |
dc.type | Article | en_US |
dc.identifier.doi | http://dx.doi.org/10.1109/JSSC.2004.831492 | - |
pubs.organisational-data | /Brunel | - |
pubs.organisational-data | /Brunel/Brunel (Active) | - |
pubs.organisational-data | /Brunel/Brunel (Active)/School of Engineering & Design | - |
Appears in Collections: | Electronic and Computer Engineering Publications Computer Science Dept of Computer Science Research Papers Dept of Electronic and Electrical Engineering Research Papers |
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