Brunel University Research Archive (BURA) >
Schools >
School of Engineering and Design >
School of Engineering and Design Research papers >

Please use this identifier to cite or link to this item: http://bura.brunel.ac.uk/handle/2438/1764

Title: Test structures to characterise a novel circuit fabrication technique that uses offset lithography
Authors: Walton, AJ
Stevenson, JTM
Fallon, M
Evans, PSA
Ramsey, BJ
Harrison, DJ
Keywords: Electric resistance measurement
Integrated circuit testing
Integrated circuit yield
Lithography
Size measurement
Publication Date: 1998
Publisher: IEEE
Citation: IEEE International conf. on microelectronic test structures, 23rd - 26th March 1998, Kanazawa, Japan.
Abstract: This paper reports on the use of microelectronic test structures to characterise a novel fabrication technique for thin-film electronic circuit boards. In this technology, circuit tracks are formed on paper-like substrates by depositing films of a metal-loaded ink via a standard lithographic printing process. Sheet resistance and line width are electrically evaluated and these quantities are compared with optical and surface profiling measurements.
URI: http://bura.brunel.ac.uk/handle/2438/1764
DOI: http://dx.doi.org/10.1109/ICMTS.1998.688032
ISBN: 0-7803-4348-4
Appears in Collections:Design
School of Engineering and Design Research papers

Files in This Item:

File Description SizeFormat
Test structures to characterise a novel circuit fabrication technique that uses offset lithography.pdf744.72 kBAdobe PDFView/Open

Items in BURA are protected by copyright, with all rights reserved, unless otherwise indicated.

 


Library (c) Brunel University.    Powered By: DSpace
Send us your
Feedback. Last Updated: September 14, 2010.
Managed by:
Hassan Bhuiyan