Please use this identifier to cite or link to this item: http://bura.brunel.ac.uk/handle/2438/2755
Title: Two-dimensional DCT/IDCT architecture
Authors: Aggoun, A
Jollah, I
Keywords: Discrete cosine transform;2D DCT;VLSI architectures;Digital circuits
Issue Date: 2003
Publisher: IET
Citation: IEE Proceedings - Computers and Digital Techniques. 150(1): 2-10
Abstract: A fully parallel architecture for the computation of a two-dimensional (2-D) discrete cosine transform (DCT), based on row-column decomposition is presented. It uses the same one dimensional (1-D) DCT unit for the row and column computations and (N2+N) registers to perform the transposition. It possesses features of regularity and modularity, and is thus well suited for VLSI implementation. It can be used for the computation of either the forward or the inverse 2-D DCT. Each 1-D DCT unit uses N fully parallel vector inner product (VIP) units. The design of the VIP units is based on a systematic design methodology using radix-2” arithmetic, which allows partitioning of the elements of each vector into small groups. Array multipliers without the final adder are used to produce the different partial product terms. This allows a more efficient use of 4:2 compressors for the accumulation of the products in the intermediate stages and reduces the number of accumulators from N to one. Using this procedure, the 2-D DCT architecture requires less than N2 multipliers (in terms of area occupied) and only 2N adders. It can compute a N x N-point DCT at a rate of one complete transform per N cycles after an appropriate initial delay.
URI: http://bura.brunel.ac.uk/handle/2438/2755
DOI: http://dx.doi.org/10.1049/ip-cdt:20030063
Appears in Collections:Electronic and Computer Engineering
Dept of Electronic and Computer Engineering Research Papers

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