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Please use this identifier to cite or link to this item: http://bura.brunel.ac.uk/handle/2438/2756

Title: Radix-2n serial–serial multipliers
Authors: Aggoun, A
Farwan, AF
Ibrahim, MK
Ashur, A
Keywords: Computer architecture
VLSI design
Digital circuits
Computer arithmetics
Publication Date: 2004
Publisher: IET
Citation: IEE Proceedings - Circuits Devices and Systems. 151(6): 503-509
Abstract: All serial–serial multiplication structures previously reported in the literature have been confined to bit serial–serial multipliers. An architecture for digit serial–serial multipliers is presented. A set of designs are derived from the radix-2n design procedure, which was first reported by the authors for the design of bit level pipelined digit serial–parallel structures. One significant aspect of the new designs is that they can be pipelined to the bit level and give the designer the flexibility to obtain the best trade-off between throughput rate and hardware cost by varying the digit size and the number of pipelining levels. Also, an area-efficient digit serial–serial multiplier is proposed which provides a 50% reduction in hardware without degrading the speed performance. This is achieved by exploiting the fact that some cells are idle for most of the multiplication operation. In the new design, the computations of these cells are remapped to other cells, which make them redundant. The new designs have been implemented on the S40BG256 device from the SPARTAN family to prove functionality and assess performance.
URI: http://bura.brunel.ac.uk/handle/2438/2756
DOI: http://dx.doi.org/10.1049/ip-cds:20040412
Appears in Collections:School of Engineering and Design Research papers
Electronic and Computer Engineering

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