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Please use this identifier to cite or link to this item: http://bura.brunel.ac.uk/handle/2438/2740

Title: Bit-level pipelined digit-serial array processors
Authors: Aggoun, A
Ibrahim, MK
Ashur, A
Keywords: Computer architecture
Computer arithmetics
Digital circuits
Digit-Serial
Hardware
VLSI architectures
Publication Date: 1998
Publisher: IEEE
Citation: IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, 45(7): 857-868
Abstract: A new architecture for high performance digit-serial vector inner product (VIP) which can be pipelined to the bit-level is introduced. The design of the digit-serial vector inner product is based on a new systematic design methodology using radix-2n arithmetic. The proposed architecture allows a high level of bit-level pipelining to increase the throughput rate with minimum initial delay and minimum area. This will give designers greater flexibility in finding the best tradeoff between hardware cost and throughput rate. It is shown that sub-digit pipelined digit-serial structure can achieve a higher throughput rate with much less area consumption than an equivalent bit-parallel structure. A twin-pipe architecture to double the throughput rate of digit-serial multipliers and consequently that of the digit-serial vector inner product is also presented. The effect of the number of pipelining levels and the twin-pipe architecture on the throughput rate and hardware cost are discussed. A two's complement digit-serial architecture which can operate on both negative and positive numbers is also presented.
URI: http://bura.brunel.ac.uk/handle/2438/2740
DOI: http://dx.doi.org/10.1109/82.700933
ISSN: 1057-7130
Appears in Collections:Electronic and Computer Engineering
Dept of Electronic and Computer Engineering Research Papers

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