Please use this identifier to cite or link to this item: http://bura.brunel.ac.uk/handle/2438/6018
Title: A VLSI architecture of JPEG2000 encoder
Authors: Liu, L
Chen, N
Meng, H
Zhang, L
Wang, Z
Chen, H
Keywords: VLSI;JPEG2000;Image Compression
Issue Date: 2004
Publisher: IEEE
Citation: IEEE Journal of Solid-State Circuits, 39(11), 2032 - 2040, Nov 2004
Abstract: This paper proposes a VLSI architecture of JPEG2000 encoder, which functionally consists of two parts: discrete wavelet transform (DWT) and embedded block coding with optimized truncation (EBCOT). For DWT, a spatial combinative lifting algorithm (SCLA)-based scheme with both 5/3 reversible and 9/7 irreversible filters is adopted to reduce 50% and 42% multiplication computations, respectively, compared with the conventional lifting-based implementation (LBI). For EBCOT, a dynamic memory control (DMC) strategy of Tier-1 encoding is adopted to reduce 60% scale of the on-chip wavelet coefficient storage and a subband parallel-processing method is employed to speed up the EBCOT context formation (CF) process; an architecture of Tier-2 encoding is presented to reduce the scale of on-chip bitstream buffering from full-tile size down to three-code-block size and considerably eliminate the iterations of the rate-distortion (RD) truncation.
Description: Copyright @ 2004 IEEE
URI: http://bura.brunel.ac.uk/handle/2438/6018
DOI: http://dx.doi.org/10.1109/JSSC.2004.831492
ISSN: 0018-9200
Appears in Collections:Electronic and Computer Engineering
Publications
Computer Science
Dept of Computer Science Research Papers
Dept of Electronic and Computer Engineering Research Papers

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