Please use this identifier to cite or link to this item: http://bura.brunel.ac.uk/handle/2438/12330
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dc.contributor.authorKalganova, T-
dc.contributor.authorMiller, J-
dc.contributor.authorLipnitskaya, N-
dc.coverage.spatialFukuoka, Japan-
dc.coverage.spatialFukuoka, Japan-
dc.date.accessioned2016-03-10T15:16:43Z-
dc.date.available1998-
dc.date.available2016-03-10T15:16:43Z-
dc.date.issued1998-
dc.identifier.citationThe 7th Workshop on Post-Binary Ultra Large Scale Integration Systems (ULSI’98) in association with ISMVL, pp. 27 - 29, 1998en_US
dc.identifier.urihttp://bura.brunel.ac.uk/handle/2438/12330-
dc.description.abstractIn this paper a gate-level evolvable hardware technique for designing multiple-valued (MV) circuits, which is easily adapted for the different types of MV gates associated with operations corresponding to different algebra types and can include other more complex logical expressions (e.g.T-gate) is proposed. The technique is based on evolving the functionality and connectivity of a rectangular array of logic cells. The evolved 3-valued 1- digit adder with carry circuit is examined as an example. The issue of choosing the optimal set of MV gates used to evolve circuit is also discussed.en_US
dc.description.sponsorshipProf. Vlad P. Shmerko and to prof. C. Moragaen_US
dc.format.extent27 - 29-
dc.language.isoenen_US
dc.publisherCiteseeren_US
dc.sourcethe 7th Workshop on Post-Binary Ultra Large Scale Integration Systems (ULSI'98)-
dc.sourcethe 7th Workshop on Post-Binary Ultra Large Scale Integration Systems (ULSI'98)-
dc.subjectMVen_US
dc.subjectEvolvable hardwareen_US
dc.subjectLogic designen_US
dc.subjectCombinational MV circuitsen_US
dc.titleMultiple-valued combinational circuits synthesized using evolvable hardware approachen_US
dc.typeConference Paperen_US
dc.relation.isPartOfProc. of the 7th Workshop on Post-Binary Ultra Large Scale Integration Systems (ULSI’98) in association with ISMVL-
pubs.publication-statusPublished-
pubs.publication-statusPublished-
pubs.start-date1998-05-
pubs.start-date1998-05-
Appears in Collections:Dept of Electronic and Electrical Engineering Research Papers

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