Please use this identifier to cite or link to this item: http://bura.brunel.ac.uk/handle/2438/13231
Title: Emulation of a prototype FPGA track finder for the CMS Phase-2 upgrade with the CIDAF emulation framework
Authors: Amstutz, C
Ball, FA
Balzer, MN
Brooke, J
Calligaris, L
Cieri, D
Clement, EJ
Hall, G
Harbaum, TR
Harder, K
Hobson, PR
Iles, GM
James, T
Manolopoulos, K
Matsushita, T
Morton, AD
Newbold, D
Paramesvaran, S
Pesaresi, M
Reid, ID
Rose, AW
Sander, O
Schuh, T
Shepherd-Themistocleous, C
Shtipliyski, A
Summers, SP
Tapper, A
Tomalin, I
Uchida, K
Vichoudis, P
Weber, M
Keywords: LHC;HL-LHC;CMS;Phase-2 upgrade;Track trigger;Hough transform;Emaulation;FPGA;VHDL;CIDAF
Issue Date: 2016
Publisher: IEEE
Citation: IEEE-NPSS Real Time Conference, RT, (2016)
Abstract: The CMS collaboration is preparing a major upgrade of its detector, so it can operate during the high luminosity run of the LHC from 2026. The upgraded tracker electronics will reconstruct the trajectories of charged particles within a latency of a few microseconds, so that they can be used by the level-1 trigger. An emulation framework, CIDAF, has been developed to provide a reference for a proposed FPGA-based implementation of this track finder, which employs a Time-Multiplexed (TM) technique for data processing.
URI: http://bura.brunel.ac.uk/handle/2438/13231
DOI: http://dx.doi.org/10.1109/RTC.2016.7543110
ISBN: 9781509020140
Appears in Collections:Dept of Electronic and Computer Engineering Research Papers

Files in This Item:
File Description SizeFormat 
Fulltext.pdf1.12 MBAdobe PDFView/Open


Items in BURA are protected by copyright, with all rights reserved, unless otherwise indicated.