Please use this identifier to cite or link to this item: http://bura.brunel.ac.uk/handle/2438/16691
Title: Pipelined photonic analog-to-digital converter
Authors: Abdollahi, S
Al-Raweshidy, H
Owens, T
Keywords: Analog to Digital Converter (ADC);Photonic Analog-to-Digital Converter (PADC);Data Conversion
Issue Date: 2018
Citation: Journal of Optics
Abstract: Electronic analog to digital converters (EADCs) face serious challenges when the root mean square timing jitter of the sampling pulse is less than a femtosecond. This restriction limits the maximum allowable sampling frequency of an EADC. In photonic analog-to-digital conversion (PADC), using a mode locked laser as a sampling source limits the sampling frequency timing jitter only at sub-femtosecond levels. The current architectures for PADC use photonic techniques either for sampling or for quantization. Consequently, current PADC architectures are not suitable for higher frequency applications because of the limitations of their electronic components. In this paper, the feasibility of implementing concept architecture for a fully photonic pipelined ADC is analyzed and evaluated to provide a design for an 8-bit pipelined PADC, the performance of which is investigated through modeling and simulation. The 8-bit pipelined PADC's effective number of bits is shown to be 4.34 bits at 200 gigasample per second.
URI: http://bura.brunel.ac.uk/handle/2438/16691
DOI: https://doi.org/10.1088/2040-8986/aad922
ISSN: 2040-8978
2040-8986
Appears in Collections:Dept of Electronic and Computer Engineering Research Papers

Files in This Item:
File Description SizeFormat 
FullText.pdf2.15 MBAdobe PDFView/Open


Items in BURA are protected by copyright, with all rights reserved, unless otherwise indicated.