Multiple-valued combinational circuits synthesized using evolvable hardware approach

Abstract

In this paper a gate-level evolvable hardware technique for designing multiple-valued (MV) circuits, which is easily adapted for the different types of MV gates associated with operations corresponding to different algebra types and can include other more complex logical expressions (e.g.T-gate) is proposed. The technique is based on evolving the functionality and connectivity of a rectangular array of logic cells. The evolved 3-valued 1- digit adder with carry circuit is examined as an example. The issue of choosing the optimal set of MV gates used to evolve circuit is also discussed.