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Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Walton, AJ | - |
dc.contributor.author | Stevenson, JTM | - |
dc.contributor.author | Fallon, M | - |
dc.contributor.author | Evans, PSA | - |
dc.contributor.author | Ramsey, BJ | - |
dc.contributor.author | Harrison, DJ | - |
dc.coverage.spatial | 6 | en |
dc.date.accessioned | 2008-02-29T16:19:10Z | - |
dc.date.available | 2008-02-29T16:19:10Z | - |
dc.date.issued | 1998 | - |
dc.identifier.citation | IEEE International conf. on microelectronic test structures, 23rd - 26th March 1998, Kanazawa, Japan. | en |
dc.identifier.isbn | 0-7803-4348-4 | - |
dc.identifier.uri | http://bura.brunel.ac.uk/handle/2438/1764 | - |
dc.description.abstract | This paper reports on the use of microelectronic test structures to characterise a novel fabrication technique for thin-film electronic circuit boards. In this technology, circuit tracks are formed on paper-like substrates by depositing films of a metal-loaded ink via a standard lithographic printing process. Sheet resistance and line width are electrically evaluated and these quantities are compared with optical and surface profiling measurements. | en |
dc.format.extent | 762590 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.language.iso | en | - |
dc.publisher | IEEE | en |
dc.subject | Electric resistance measurement | en |
dc.subject | Integrated circuit testing | - |
dc.subject | Integrated circuit yield | - |
dc.subject | Lithography | - |
dc.subject | Size measurement | - |
dc.title | Test structures to characterise a novel circuit fabrication technique that uses offset lithography | en |
dc.type | Conference Paper | en |
dc.identifier.doi | http://dx.doi.org/10.1109/ICMTS.1998.688032 | - |
Appears in Collections: | Design Brunel Design School Research Papers |
Files in This Item:
File | Description | Size | Format | |
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Test structures to characterise a novel circuit fabrication technique that uses offset lithography.pdf | 744.72 kB | Adobe PDF | View/Open |
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