Development of generic testing strategies for mixed-signal integrated circuits

Please use this identifier to cite or link to this item: http://bura.brunel.ac.uk/handle/2438/1800

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DC Field	Value	Language
dc.contributor.author	Pritchard, TI	-
dc.contributor.author	Evans, PSA	-
dc.contributor.author	Taylor, D	-
dc.coverage.spatial	3	en
dc.date.accessioned	2008-03-07T15:40:40Z	-
dc.date.available	2008-03-07T15:40:40Z	-
dc.date.issued	1992	-
dc.identifier.citation	IEE Proc. Part G, Volume 139, No.2, April 1992. Pages 231 - 233.	en
dc.identifier.issn	0956-3768	-
dc.identifier.uri	http://bura.brunel.ac.uk/handle/2438/1800	-
dc.description.abstract	Describes work at the Polytechnic of Huddersfield SERC/DTI research project IED 2/1/2121 conducted in collaboration with GEC-Plessey Semiconductors, Wolfson Microelectronics, and UMIST. The aim of the work is to develop generic testing strategies for mixed-signal (mixed analogue and digital) integrated circuits. The paper proposes a test structure for mixed-signal ICs, and details the development of a test technique and fault model for the analogue circuit cells encountered in these devices. Results obtained during the evaluation of this technique in simulation are presented, and the ECAD facilities that have contributed to this and other such projects are described.	en
dc.format.extent	294251 bytes	-
dc.format.mimetype	application/pdf	-
dc.language.iso	en	-
dc.publisher	IEEE	en
dc.subject	Generic tesring; Mixed-signal ICs; Integrated crrcuits	en
dc.title	Development of generic testing strategies for mixed-signal integrated circuits	en
dc.type	Conference Paper	en
Appears in Collections:	Design Brunel Design School Research Papers

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