Circuit layout evolution: An evolvable hardware approach

Kalganova, T; Miller, J F

Please use this identifier to cite or link to this item: http://bura.brunel.ac.uk/handle/2438/2411

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DC Field	Value	Language
dc.contributor.author	Kalganova, T	-
dc.contributor.author	Miller, J F	-
dc.coverage.spatial	4	en
dc.date.accessioned	2008-06-13T15:31:58Z	-
dc.date.available	2008-06-13T15:31:58Z	-
dc.date.issued	1999	-
dc.identifier.citation	Coloquium on Evolutionary Hardware Systems, IEE Colloquium Digest. London, UK, 1999. pp. 3/1 - 3/4	en
dc.identifier.uri	http://bura.brunel.ac.uk/handle/2438/2411	-
dc.description.abstract	The evolvable hardware technique is based on evolving the functionality and connectivity of a rectangular array of logic cells in addition to the layout of this may. The evolutionary process contains two main steps. Initially the genome fitness in given by the percentage of output bits, which are correct. Once 100% functional circuits have been evolved, the number of gates actually used in the circuit is taken into account in the fitness function. This allows us to evolve circuit with 100% functionality and minimise the number of active gates in circuit structure. We perform a number of experiments to investigate the behaviour of the second fitness function and the circuit layout during evolution. We find that the gate usage is linearly related to the total number of gates in the chromosome.	en
dc.format.extent	447846 bytes	-
dc.format.mimetype	application/pdf	-
dc.language.iso	en	-
dc.publisher	IEEE	en
dc.title	Circuit layout evolution: An evolvable hardware approach	en
dc.type	Conference Paper	en
Appears in Collections:	Electronic and Computer Engineering Dept of Electronic and Electrical Engineering Research Papers

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