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Please use this identifier to cite or link to this item: http://bura.brunel.ac.uk/handle/2438/32055
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dc.contributor.authorAl-Alousi, A-
dc.contributor.authorLi, M-
dc.contributor.authorMeng, H-
dc.date.accessioned2025-09-27T07:10:36Z-
dc.date.available2025-09-27T07:10:36Z-
dc.date.issued2025-
dc.identifierORCiD: Maozhen Li https://orcid.org/0000-0002-0820-5487-
dc.identifierORCiD: Hongying Meng https://orcid.org/0000-0002-8836-1382-
dc.identifier.citationAl-Alousi, A., Li, M. and Meng, H. (2025) 'Vendor-Independent Design Space Exploration and Resource Optimisation Framework for 3D Networks-on-Chip Using Hypergraph-Genetic Algorithm Integration', IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems, 0 (accepted, in press)en_US
dc.identifier.issn0278-0070-
dc.identifier.urihttps://bura.brunel.ac.uk/handle/2438/32055-
dc.descriptionAn e-print version of the article is available at https://www.techrxiv.org/doi/full/10.36227/techrxiv.173198800.09799079 under a CC BY license. e-Prints posted on TechRxiv are preliminary reports that are not peer reviewed. They should not be regarded as conclusive, guide clinical practice/health-related behavior, or be reported in the media as established information.en_US
dc.description.abstract...en_US
dc.description.sponsorship...en_US
dc.format.extent1 - 11-
dc.language.isoen_USen_US
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.rightsCopyright © 2025 Institute of Electrical and Electronics Engineers (IEEE). Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works ( https://journals.ieeeauthorcenter.ieee.org/become-an-ieee-journal-author/publishing-ethics/guidelines-and-policies/post-publication-policies/ ).-
dc.rights.urihttps://journals.ieeeauthorcenter.ieee.org/become-an-ieee-journal-author/publishing-ethics/guidelines-and-policies/post-publication-policies/-
dc.subject3D Networks-on-Chipen_US
dc.subjectdesign spaceen_US
dc.subjectexplorationen_US
dc.subjectgenetic algorithmsen_US
dc.subjecthypergraph theoryen_US
dc.subjectresource optimisationen_US
dc.subjectSystem-on-Chipen_US
dc.titleVendor-Independent Design Space Exploration and Resource Optimisation Framework for 3D Networks-on-Chip Using Hypergraph-Genetic Algorithm Integrationen_US
dc.typeArticleen_US
dc.relation.isPartOfIEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems-
pubs.issue0-
pubs.publication-statusAccepted-
pubs.volume00-
dc.identifier.eissnPrint-Electronic-
dc.identifier.eissn1937-4151-
dc.rights.holderInstitute of Electrical and Electronics Engineers (IEEE)-
Appears in Collections:Dept of Electronic and Electrical Engineering Embargoed Research Papers

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