Innovations in arithmetic for neuromorphic computing

Abstract

The continued growth in computational demand, driven in large part by machine learning workloads, has coincided with the slowing of performance gains from semiconductor scaling alone. Therefore, additional computing power can no longer be simply obtained by using increased transistor density or clock frequency to scale standard architecture. Instead, alternative computing paradigms are required. Neuromorphic computing has emerged as one such approach, offering architectures designed to improve computational efficiency by mimicking aspects of biological neural networks such as massive parallelism, locality of memory and computation, and sparse activity. Spiking Neural Networks (SNNs) are the primary computational models executed on neuromorphic processors, processing information through temporal dynamics and sparse events rather than dense numerical operations. However, the numerical representation used to implement these dynamics remains an open design question. This thesis investigates the role of arithmetic choice in digital neuromorphic computing, with a particular focus on posit arithmetic as an alternative to conventional fixed-point and IEEE-754 floating-point formats. Rather than treating reduced precision as an optimisation problem to be mitigated against, this work adopts an arithmetic-centric perspective, evaluating whether alternative number systems can intrinsically offer improved numerical behaviour at reduced bit-widths. To this end, rather than the more common mixed-precision approach, all experiments use reduced-precision emulation throughout to simulate a neuromorphic system operating natively with the target format, providing a conservative assessment of arithmetic suitability for future neuromorphic hardware. The thesis makes three primary contributions. First, it presents a systematic study of reduced-precision arithmetic for simulating neural dynamics, using the Izhikevich neuron model across its full range of canonical firing patterns. The results demonstrate that 16-bit posit arithmetic can match or outperform IEEE-754 floating-point equivalents of equal bit-width, and in some cases 16-bit posit can match 64-bit floating-point accuracy, if combined with a simple rescaling strategy. Second, the work provides the first comprehensive evaluation of 8-bit posit arithmetic for offline SNN training using gradient-based methods. Across both frame-based and event-based datasets, 8-bit posits are shown to enable effective training without the need for mixed-precision schemes, loss scaling, or other mitigation techniques commonly required by low-precision floating-point formats. Finally, the thesis presents the first detailed analysis of arithmetic effects on online learning in SNNs using the e-prop algorithm, demonstrating that 16-bit posits enable stable training and outperform higher-precision floating-point formats, while fixed-point representations require approximately 64-bit precision to attain similar performance. Collectively, these results show that posit arithmetic can match the numerical and system level performance of larger floating point formats while using smaller bit widths and requiring fewer, if any, mitigation strategies. The designers of future digital neuromorphic architectures should therefore seriously consider including posit rather than fixed or floating point arithmetic units.