Please use this identifier to cite or link to this item: http://bura.brunel.ac.uk/handle/2438/25151
Title: Complexity-reduced hardware-based track-trigger for CMS upgrade
Authors: Ghorbani, Maziar
Advisors: Cole, J
Khan, A
Keywords: High-performance FPGA and ASIC Design;High-Level Synthesis and Hardware Acceleration;High-Luminosity Front-end Electronics;Time-Multiplexed Track Reconstruction;Particle Tracking Detector
Issue Date: 2022
Publisher: Brunel University London
Abstract: The Compact Muon Solenoid (CMS) detector at the Large Hadron Collider (LHC) is designed to study the results of proton-proton collisions. The Tracker sub-detector is designed to detect and reconstruct the trajectories of charged particles produced by the collisions. During the lifetime of the CMS detector, there have been several upgrades aimed at increasing the chance of discovering new physics through increased luminosity levels and instrumentation of advanced technology. The High-Luminosity upgrade optimises the LHC to accelerate high-energy particles with an average of 200 proton-proton interactions per bunch crossing. The Level-1 Trigger system promptly analyses and filters collisions using hardware to reduce the data volume in real-time. For the upgrade, the trigger mechanism will use a particle trajectory estimator that discriminates between particles based on their transverse momentum (pT ). Particles with pT ≥ 2 GeV/c will be transmitted to the Level-1 Track-Trigger system for trajectory reconstruction within a fixed 3 μs latency. This thesis presents a novel Hardware-based Multivariate Linear Fitter (MVLF) system focusing on robustness in tracking efficiency and reduction in logic resource usage within the specified latency. The system components are implemented in Field Programmable Gate Arrays (FPGA), targeting 16 nm FinFET UltraScale+ silicon technology. The development was performed using the High-Level Synthesis (HLS) automation tools and the Hardware acceleration platform for Application-Specific Integrated Circuits (ASIC). A firmware demonstrator has been assembled to verify the feasibility and compatibility of the scaled system with the CMS Level-1 Track-Trigger infrastructure. The system’s performance is compared to past and current system developments, and the results are presented accordingly.
Description: This thesis was submitted for the award of Doctor of Philosophy and was awarded by Brunel University London
URI: http://bura.brunel.ac.uk/handle/2438/25151
Appears in Collections:Electronic and Computer Engineering
Dept of Electronic and Computer Engineering Theses

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