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http://bura.brunel.ac.uk/handle/2438/7288
Title: | FACTPLA: Functional analysis and the complexity of testing programmable logic array |
Authors: | Abbas, Samir I |
Advisors: | Musgrave, G |
Issue Date: | 1988 |
Publisher: | Brunel University School of Engineering and Design PhD Theses |
Abstract: | A computer aided method for analyzing the testability of Programmable Logic Arrays (PLAs) is described. The method, which is based on a functional verification approach, estimates the complexity of testing a PLA according to the amount of single undetectable faults in the array structure. An analytic program (FACTPLA) is developed to predict the above complexity without analyzing the topology of the array as such. Thus, the method is technology invariant and depends only on the functionality of the PLA. The program quantitatively evaluates the effects of undetectable faults and produces some testability measures to manifest these effects. A testability profile for different PLA examples is provided and a number of suggestions for further research to establish definitely the usefulness of some functional properties for testing were made. |
Description: | This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University. |
URI: | http://bura.brunel.ac.uk/handle/2438/7288 |
Appears in Collections: | Electronic and Electrical Engineering Dept of Electronic and Electrical Engineering Theses |
Files in This Item:
File | Description | Size | Format | |
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FulltextThesis.pdf | 4.48 MB | Adobe PDF | View/Open |
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