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Title: Test structures to characterise a novel circuit fabrication technique that uses offset lithography
Authors: Walton, AJ
Stevenson, JTM
Fallon, M
Evans, PSA
Ramsey, BJ
Harrison, DJ
Keywords: Electric resistance measurement;Integrated circuit testing;Integrated circuit yield;Lithography;Size measurement
Issue Date: 1998
Publisher: IEEE
Citation: IEEE International conf. on microelectronic test structures, 23rd - 26th March 1998, Kanazawa, Japan.
Abstract: This paper reports on the use of microelectronic test structures to characterise a novel fabrication technique for thin-film electronic circuit boards. In this technology, circuit tracks are formed on paper-like substrates by depositing films of a metal-loaded ink via a standard lithographic printing process. Sheet resistance and line width are electrically evaluated and these quantities are compared with optical and surface profiling measurements.
ISBN: 0-7803-4348-4
Appears in Collections:Design
Dept of Design Research Papers

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