Resource optimisation of networks on chip for high performance system on chip applications

Abstract

This thesis presents a novel methodology for resource optimisation of 3D Network-on-Chip (NoC) architectures in High-Performance System-on-Chip (SoC) applications. The proposed approach combines hypergraph-based modelling and genetic algorithm optimisation to efficiently explore the design space and identify optimal combinations of topology and routing algorithms tailored to specific application requirements. Two compute-intensive, yet different use cases were chosen to validate the approach; namely, the double SHA256 attack as applied to Bitcoin mining, and real-time facial recognition. In addition to hypergraph modelling and GA optimisation, a unique aspect of this work is the development of the Performance-to-Cost-Ratio function concept, as an effective, yet simple method to steer the fitness evaluation during the optimisation phase. In contrast to existing research that focuses on narrow perspectives of the problem, this work offers a more holistic approach, by considering the interplay of routing strategies, buffer and message sizing, bandwidth, and latency factors, together with resource utilisation. The results and insights obtained contribute to the overall understanding of the design and optimisation of 3D NoC architectures and their impact on system performance and resource utilisation. Three specific research questions are addressed. First, the effective utilisation of hypergraphs as a design and implementation space exploration modelling tool for 3D NoCs; Second, is the justification and use of genetic algorithms as an optimisation technique, once a suitable topology is identified; and finally, the combination of the ideas of hypergraph modelling and GA optimisation as framework in high-performance SoC designs employing 3D NoCs. Extensive simulations and comparative analyses carried out showed significant performance improvements in latency, throughput, bandwidth and resource utilisation, versus the chosen 3D Mesh baseline architecture. The optimised architectures also lead to an observable energy efficiency characteristic, when tested on an actual FPGA implementation. The proposed methodology provides a systematic and automated design space exploration and optimisation approach in the domain, eliminating the need for manual design space exploration, this enabling architects and designers to make informed decisions based on the specific requirements of the target application, from the onset. The insights and techniques presented in this thesis have far reaching implications for developing efficient and scalable NoC solutions in the era of kilo- and mega-core SoC applications.